1. Field of the Invention
The present invention relates to a data transmission system, a corresponding method, a data sending apparatus, and a data receiving apparatus, and in particular, relates to those for performing high-speed transmission by effectively using a band of a transmission path between information processing apparatuses.
2. Description of the Related Art
Japanese patent No. 3,719,413 (Patent Document 1) proposes a technique by which a signal phase includes information so as to enlarge a noise margin and implement high-frequency transmission. The relevant high-frequency transmission technique will be explained below.
FIG. 17 is a block diagram of a data transmission system disclosed as a first embodiment in Patent Document 1. In FIG. 17, a data sending apparatus 1 has delay circuits 11 and 12, and multiplexers 13 and 14.
The delay circuit 11 delays a signal CLK, which is supplied from an external device and has a base frequency, by a unit of time, and outputs the delayed signal.
The delay circuit 12 has a delaying time twice as much as that provided by the delay circuit 11, so that it delays the signal CLK by twice the unit of time, and outputs the delayed signal.
The multiplexer 13 always selects the signal output from the delay circuit 11, and outputs the selected signal as a reference signal REF. The multiplexer 13 is used for capturing the time required for the processing of the multiplexer 14, and for synchronizing with the signal output from the multiplexer 14.
The multiplexer 14 selects one of the signal CLK or the signal output from the delay circuit 12 based on data DIN, and outputs the selected signal as a signal DATA.
As shown in FIG. 18, the signal CLK and the signal output from the delay circuit 12 are input into the multiplexer 14. As shown in FIG. 19, when data DIN has a value of “0”, the signal CLK is selected and output as transmission data DATA. When data DIN has a value of “1”, the signal output from the delay circuit 12 is selected and output as the transmission data DATA.
When data DIN has a value of “0”, the phase of the transmission data DATA is more advanced than the reference signal REF by the unit of time. When data DIN has a value of “1”, the phase of the transmission data DATA is more delayed than the reference signal REF by the unit of time.
In accordance with the above structure, the reference signal REF and the transmission data DATA are output from the data sending apparatus 1.
In FIG. 17, a data receiving apparatus, into which the reference signal REF and the transmission data DATA are input, has a phase comparator 21, and an RS latch 22.
The phase comparator 21, into which the reference signal REF and the transmission data DATA are input, and detects a phase difference between the reference signal REF and the transmission data DATA. When the phase of the transmission data DATA is more advanced than the reference signal REF, a phase advance detection signal R having a pulse width corresponding to the phase difference is output. When the phase of the transmission data DATA is more delayed than the reference signal REF, a phase delay detection signal S having a pulse width corresponding to the phase difference is output.
That is, when the phase of the transmission data DATA is more advanced than the phase of the reference signal REF by the unit of time, the phase advance detection signal R having a pulse width corresponding to the unit of time is output. When the phase of the transmission data DATA is more delayed than the phase of the reference signal REF by the unit of time, the phase delay detection signal S having a pulse width corresponding to the unit of time is output.
The phase delay detection signal S and the phase advance detection signal R are input into the RS latch 22. When the phase advance detection signal R is applied to a reset input terminal, a data reproduction signal DOUT is set to the level “0”. When the phase delay detection signal S is applied to the reset input terminal, a data reproduction signal DOUT is set to the level “1”. The data reproduction signal DOUT is obtained as described above.
In the data transmission system as the first embodiment of Patent Document 1, the signal phase has information so as to enlarge the noise margin, thereby implementing high-frequency transmission. However, the first embodiment requires a dedicated transmission path for transmitting the reference signal REF as a reference for phase advance or delay of transmission data.
Accordingly, Patent Document 1 also discloses a third embodiment in which the reference signal REF as a reference for the phase advance or delay of transmission data is reproduced on the receiving side, so as to reduce the dedicated transmission path used for transmitting the reference signal REF.
That is, in the third embodiment of Patent Document 1, as shown in FIG. 20, a PLL (phase locked loop) circuit 20 is added to the data receiving apparatus 2, and the PLL circuit 20 generates the reference signal REF by using the transmission data DATA. Similar to the first embodiment of Patent Document 1, the reference signal REF generated by the PLL circuit 20 is input into a terminal of the phase comparator 21, and used as a reference in phase comparison for the transmission data DATA.
However, since the signal phase has information in the third embodiment of Patent Document 1, the relevant data has a large DC (direct current) component. Therefore, if the signal sign “0” or “1” continues for a long time, the control of the PLL circuit 20 is drawn by a phase corresponding to one of the two signs, so that the relevant data cannot be reproduced. Accordingly, in the third embodiment, in order that the time in which the signal sign “0” or “1” continues is sufficiently short in comparison with the response time of the PLL circuit 20, the data DIN applied to the multiplexer 14 should be encoded so as to include no DC component, and to satisfy a condition such that the time in which the signal sign “0” or “1” continues is sufficiently short in comparison with the response time of the PLL circuit 20.
In order to satisfy such restrictions, when the relevant data is encoded using an encoding method (e.g., 8B/10B encoding) by which “0” or “1” continues within a limited time, and is transmitted, the number of bits of the transmission data increases, which also increases the relevant latency.